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| 74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS s s s s s s s s s s s HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY SOP TSSOP ORDER CODES PACKAGE SOP TSSOP TUBE 74LVX373M T&R 74LVX373MTR 74LVX373TTR DESCRIPTION The 74LVX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. PIN CONNECTION AND IEC LOGIC SYMBOLS When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. July 2001 1/10 74LVX373 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16,19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 LE GND VCC NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs 3-State Outputs Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE* L H X : Don't Care Z : High Impedance * : Q Outputs are Latched at the time when the LE INPUT is taken low logic level LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 74LVX373 ABSOLUTE MAXIMUM RATINGS Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol V CC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 2) (VCC = 3V) Parameter Value 2 to 3.6 0 to 5.5 0 to VCC -55 to 125 0 to 100 Unit V V V C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 VOL Low Level Output Voltage 2.0 3.0 3.0 I OZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 3.6 3.6 3.6 IO=-50 A IO=-50 A IO=-4 mA IO=50 A IO=50 A IO=4 mA VI = VIH or VIL VO = VCC or GND VI = 5V or GND VI = VCC or GND TA = 25C Min. 1.5 2.0 2.4 Value -40 to 85C Min. 1.5 2.0 2.4 -55 to 125C Min. 1.5 2.0 2.4 Unit Typ. Max. Max. Max. V 0.5 0.8 0.8 VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage V IL 0.5 0.8 0.8 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.25 0.1 4 2.0 3.0 1.9 2.9 2.48 0.5 0.8 0.8 1.9 2.9 2.4 0.1 0.1 0.44 2.5 1 40 V VOH V 0.1 0.1 0.55 5 1 40 A A A 3/10 V II ICC 74LVX373 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 0.3 3.3 -0.8 C L = 50 pF 2.0 -0.3 V Max. 0.8 Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit VOLP V OLV V IHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 3.3 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 2.7 2.7 3.3 tPLH tPHL Propagation Delay Time D to Q (*) Value TA = 25C Min. Typ. 7.5 10.0 6.8 9.3 7.7 10.2 5.8 8.5 7.7 10.2 6.0 8.5 9.8 8.2 Max. 14.5 18.0 10.3 13.8 15.0 18.5 9.7 13.2 15.0 18.5 9.7 13.2 18.0 12.8 6.5 5.0 6.0 4.0 1.0 1.0 0.5 0.5 1.0 1.0 -40 to 85C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 17.5 21.0 12.0 15.5 18.5 22.0 11.5 15.0 18.5 22.0 11.5 15.0 21.0 14.5 7.5 5.0 6.0 4.0 1.0 1.0 1.5 1.5 -55 to 125C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 18.5 22.0 13.0 16.5 19.5 23.0 12.5 16.0 19.5 23.0 12.5 16.0 22.0 15.5 7.5 5.0 6.0 4.0 1.0 1.0 1.5 1.5 ns ns ns ns ns ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 15 50 15 50 50 50 50 50 50 50 50 50 50 50 tPLH tPHL Propagation Delay Time LE to Q 3.3 (*) 2.7 2.7 3.3 (*) tPZL tPZH Output Enable Time 3.3 (*) 2.7 2.7 3.3 (*) tPLZ tPHZ tW tS th tOSLH tOSHL 3.3 (*) 2.7 3.3 2.7 (*) Output Disable Time LE pulse Width, HIGH Setup Time D to LE HIGH or LOW Hold Time D to LE HIGH or LOW Output to Output Skew Time (note 1,2) 3.3 (*) 2.7 3.3 (*) 2.7 3.3 2.7 (*) 3.3 (*) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V 4/10 74LVX373 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 fIN = 10MHz TA = 25C Min. Typ. 5 10 40 Max. Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit CIN C OUT C PD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit) TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ C L =15/50pF or equivalent (includes jig and probe capacitance) R L = R1 = 1K or equivalent R T = ZOUT of pulse generator (typically 50) SWITCH Open VCC GND 5/10 74LVX373 WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/10 74LVX373 WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74LVX373 SO-20 MECHANICAL DATA mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.020 13.00 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch PO13L 8/10 74LVX373 TSSOP20 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.260 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0087225C 9/10 74LVX373 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com 10/10 |
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